The present invention disclosed herein relates to a semiconductor memory device, and an input/output (I/O) drive circuit of the semiconductor memory device.
FIG. 1 illustrates a semiconductor memory device 10. Referring to FIG. 1, the semiconductor memory device 10 includes a plurality of I/O drive circuits DQ0 to DQ6, a plurality of internal voltage generation circuits 11 supplying internal voltages to the I/O drive circuits DQ0 to DQ6, and decoupling capacitors (DECAPs). The DECAPs supply auxiliary operational currents to the I/O drive circuits DQ0 to DQ6 when the voltage levels of input data to the I/O drive circuits DQ0 to DQ6 vary from low to high or from high to low. The internal voltage generation circuits 11 supply main operational currents to the I/O drive circuits DQ0 to DQ6. However, since the internal voltage generation circuits 11 have a slow response time, the operational currents supplied from the internal voltage generation circuits 11 to the I/O drive circuits DQ0 to DQ6 can be temporarily insufficient when the voltage levels of input data to the I/O drive circuits DQ0 to DQ6 are varied. Here, the slow response time of the internal voltage generation circuits 11 means that the internal voltage generation circuits 11 cannot supply sufficient currents. For this reason, the DECAPs are provided to supply auxiliary currents to the I/O drive circuits DQ0 to DQ6.
FIG. 2 illustrates an exemplary structure of an output drive circuit 100 of the I/O drive circuits DQ0 to DQ6 of the semiconductor memory device of FIG. 1. Referring to FIG. 2, the output drive circuit 100 includes a first output circuit 110 and a second output circuit 120. Data are input to the output drive circuit 100 through an input node Q. Then, the data are processed by the first output circuit 110 and the second output circuit 120 and are output from the output drive circuit 100 through an output node OUT. Although the first output circuit 110 outputs the data without a delay, the second output circuit 120 outputs the data after delaying the data for a predefined time so as to prevent distortion of the data in a channel. That is, when the data are transmitted immediately without a delay, reflection waves can increase.
Referring to FIG. 2, the output drive circuit 100 operates as follows. For example, it is assumed that data including a low to high voltage level transition are input to the input node Q. In the first output circuit 110, the data are transmitted to an n-channel metal oxide semiconductor (NMOS) transistor N2 through a first path, and the NMOS transistor N2 is turned on responsive to the data. Inverters 112 and 113 may be disposed along the first path. In the second output circuit 120, the data are transmitted to an n-channel metal oxide semiconductor (NMOS) transistor N4 through a second path, and the NMOS transistor N4 is turned on responsive to the data. A delay circuit 121 and inverters 122 and 123 may be disposed along the second path. The delay circuit 121 may delay the data for a predefined time (e.g., for about 200 ps to about 300 ps). Therefore, the NMOS transistor N4 is turned on a predefined time later after the NMOS transistor N2 is turned on. When a high-level voltage Vg is applied to gates of NMOS transistors N1 and N3, the voltage level of a PAD changes from VTERM to VTERM-(I*RTERM), where I denotes a current at the PAD that is equal to the sum of currents from the NMOS transistors N2 and N4. The amount of the current I may be controlled by the voltage Vg.
When the voltage level of the input node Q of the output drive circuit 100 changes from high to low (or low to high), the DECAPs are used to make up for insufficient current supply. However, in this case, output power noise increases since the voltage levels of the DECAPs are not constant.
Meanwhile, when the voltage level of input data changes from high to low, the output drive circuit 100 operates as follows. In the first output circuit 110, the input data are transmitted to the NMOS transistor N2 through the first path and turn off the NMOS transistor N2. In the second output circuit 120, the input data are transmitted to the NMOS transistor N4 through the second path and turn off the NMOS transistor N4. Here, the input data are delayed for a predefined time when transmitted along the second path to a gate of the NMOS transistor N4 although the input data are not delayed in the first path. Therefore, the NMOS transistor N4 is turned off a predefined time later after the NMOS transistor N2 is turned off. Here, the voltage level of the PAD is VTERM. Even though an even number of inverters are shown in the first output circuit (e.g., 112 and 113) and an even number of inverters are shown in the second output circuit (e.g., 122 and 123), if an odd number of inverters are used, the same problem can occur on a transition of the input data in the opposite direction.